Meansof synthesis of high-performance FPGA-type PLD and FPGA, optimized interms of ease of use and high quality results. Supports amulti-million-programmable systems-on-Chip (FPSoC) the last generation.
PrecisionRTL Synthesis receive input on the project as a description in VHDL orVerilog and implements logic synthesis with the defined limits, based onbuilt-in libraries of manufacturers. The package has a built-in statictiming analysis, the ability to analyze and debug in an incrementalmode, and an intuitive user interface makes it easy to manage theprocess of fusion as an experienced engineer, and beginner. PrecisionRTL Synthesis includes a unique optimization algorithm - ArchitectureSignature Extraction (ASE), which automatically selects the mostcritical in the project area, limiting the overall system performance,such as finite automata, logical paths between the various levels ofdesign hierarchy or logical path with a very large number ofcombinational logic . ASE algorithm uses heuristic analysis in anautomatic mode to reduce the size of the project and increase itsproductivity without the need for manual intervention. It supports allseries of crystals Xilinx (including the Virtex-7), Altera, Actel andLattice.
Year / Date of Release: 2011
Version: 2011a Build 1961
Developer: Mentor Graphics
Bit depth: 32bit
Compatibility with Vista: complete
Compatible with Windows 7: complete